1. Field of the Invention
This invention relates to a method for manufacturing a full-feature EEPROM (Electrical Erasable and Programmable Read Only Memory) cell, and more particularly to a manufacturing method for a full-feature EEPROM cell which allows the device to be made smaller than is possible by conventional manufacturing techniques.
2. Technical Description
A conventional full-feature EEPROM cell comprises a selective-gate transistor 10 and a stacked-gate transistor 12 which are made on a substrate 1 as shown in FIG. 1, wherein the selective-gate transistor 10 comprises a heavily n-doped drain region 14, a heavily n-doped source region 16, a selective gate 104 formed on substrate 1 and overlying a portion of substrate 1 between drain region 14 and source region 16, and a gate oxide 102 between substrate 1 and selective gate 104. Stacked-gate transistor 12 comprises heavily n-doped drain region 16 (i.e., the source of selective-gate transistor 10), a heavily n-doped source region 18, a stacked gate including a floating gate 124, a dielectric layer 126 and a control gate 128 formed on substrate 1 and overlying a portion of substrate 1 between drain region 16 and source region 18, and a tunnel oxide 122 between substrate 1 and floating gate 124. The kind of EEPROM cell shown in FIG. 1 is referred to as "full-featured" since stacked-gate transistor 12 of the EEPROM can be erased, programmed, and is free from problems due to over-erasure of stacked-gate transistor 12 in an alternative range of a byte or multiple bytes by controlling selective-gate transistor 10.
However, the dimensions of the conventional full-feature EEPROM cell cannot be scaled down because the selective-gate transistor and the stacked-gate transistor are manufactured separately in conventional manufacturing procedures.